1. Field of the Invention
The present invention relates to a semiconductor read only memory device such as a mask ROM which employs flat type memory cells, and more particularly to a semiconductor memory device which is intended to inhibit a voltage drop of main bit lines.
2. Description of the Related Art
FIG. 1 is a block diagram showing a conventional semiconductor memory device.
The conventional semiconductor memory device shown in FIG. 1 is a mask ROM employing flat type memory cells. A plurality of sub-bit lines and a plurality of word lines are arranged to be perpendicularly intersected each other. Each of intersections thereof is provided with one memory cell. Every two sub-bit lines are connected to one main bit line, while one sub-bit line following the every two sub-bit lines skips. In this manner, a memory cell array 111 is constructed. Also, an address designating section (not shown) is provided to select a specific memory cell via main bit lines, sub-bit lines and word lines. The address designating section is provided with an address buffer 102, a Y decoder 104, a bank decoder 105, a word decoder 106, a virtual GND decoder 107, a Y selector 110, a virtual GND selector 112 and the like. Furthermore, the conventional semiconductor memory device is provided with a data output section, which outputs a signal in response to data stored in the memory cell selected by the address designating section. The data output section includes a sense circuit 109, an output buffer 113, a charge circuit 108 and the like.
The conventional semiconductor memory device constructed as explained in the above has characteristics that the main bit line, the sub-bit line and the word line become active by a control signal, and the word line become active after a predetermined time is passed after the main bit lines and the sub-bit lines are active at the same time. This is because very large number of gate capacities is connected to the word lines as compared to the main bit lines and the sub-bit lines. For example, such a semiconductor memory device is disclosed in Japanese Patent Laid-Open Nos. hei 4-311900 and hei 9-265791.
However, the conventional semiconductor memory device cannot operate at a sufficiently high speed, since it includes several defects as follows:
Because a large number of gate capacities is connected to the word lines, delay time thereof is long. Due to this, there may be a malfunction either if an ON bit memory cell is selected or if an OFF bit memory cell is selected.
FIG. 2 is a timing chart showing the operations of the conventional semiconductor memory device shown in FIG. 1. For example, if the ON bit memory cell is selected, the main bit line (node SC) is charged due to the activation of the sense circuit 109 and the Y selector 110. However, because the delay time of word lines (word line decoding signal WD) is long, the main bit line (node SC) will be charged to the high level. As a result, though the expected value (true value) of the main bit line (node SC) is set to the low level when the ON bit memory cell is selected, a differential amplifier incorporated in the sense circuit 109 malfunctions and thereby outputs the high level in a first malfunction period.
FIG. 3 is a circuit diagram showing banks present in the conventional semiconductor memory device shown in FIG. 1. For example, it is assumed that memory cells MC0 and MC3 are OFF bits and memory cells MC1 and MC2 are ON bits. And, when the OFF bit memory cell MC0 is selected, the main bit line D0 is charged to the high level. In this case, because the word line WD0 is activated, the memory cells MC1 and MC2, which are adjacent to the memory cell MC0 also become conductive state. As a result, current also flows through sub-bit lines B02 and B03 which are set to the GND level, as indicated by arrows. Therefore, the voltage of the main bit line D0 is transiently dropped in a second malfunction period.
The capacity of the sub-bit lines B02 and B03 is as minute as 100 fF per each at most. However, because the sensitivity of the sense circuit 109 is high, even though the expected value is in the high level, it is detected as the low level (false data) due to the voltage drop. Therefore, surplus delay time in returning to the true data is generated.
Strictly, the existence of the malfunctions at the time when selecting an ON bit memory cell and at the time when selecting an OFF bit memory cell depends on the design technique of reference level VRA. However, in FIG. 2, the fact that the main bit line (node SC) has been set to the state of false data (in a first malfunction period) and is to be turned to the false data (in a second malfunction period) forms a problem, in themselves.
And, in view of noise margin in the design, frequent level variations (e.g., from high level to low level, and then to high level) of the main bit line (node SC) are not desired. Furthermore, it is not easy to highly increase the speed of word line decoding signal WD, because it is contrary to the high integration.
Additionally, there are cases that the main bit line (node SC) is connected to the charge circuit 109, and the main bit line (node SC) is connected to the virtual GND line VRG, in response to a selected address. For this reason, if reading is repeated plural times, the initial value of the main bit line (node SC) becomes indefinite.
FIG. 4 is a timing chart showing the operation of the conventional semiconductor memory device shown in FIG. 1. It is assumed that the memory cell MC0 is selected in a first reading period and the memory cell MC4 is selected in a second reading period. In this case, a main bit line D3 is charged in the first reading period and discharged in the second reading period. The main bit line selected in the second reading period is a main bit line D1. Because the main bit line D3 and the main bit line D1 adjoin each other, a coupling capacitance exists therebetween. And, signals flowing in these main bit lines are opposite phases each other. Therefore, crosstalk, which increases delay time, is generated.
With reference to FIG. 3, the necessity of the charge circuit 108 is explained. It is assumed that the selected memory cell MC0 is OFF bit and memory cells MC1 to MC7 are ON bits. In this case, if the memory cell MC0 is selected, non-selected memory cells MC1 to MC7 become conductive state. For this reason, sub-bit lines B04 to B10 are charged. As a result, the voltage of node SC of main bit line D0 (the expected value of which is high level) will be dropped and the reading speed will be decreased. In order to prevent this, the charge circuit 108 applies a voltage to the node PC.
It is the object of the present invention to provide a semiconductor memory device that can inhibit a voltage drop of main bit lines when data is read or when sub-bit lines are charged.
According to one aspect of the present invention, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of main bit lines and a plurality of word lines that are perpendicularly intersected each other, and a plurality of memory cells provided at each of intersections between the main bit lines and word lines one by one. The semiconductor memory device further comprises a sense circuit which activates the main bit lines, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among the plurality of memory cells, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.
According to another aspect of the present invention, a semiconductor memory device comprises a memory cell array. The memory cell array has a plurality of sub-bit lines and a plurality of word lines that are perpendicularly intersected each other, a plurality of memory cells provided at each of intersections between the sub-bit lines and word lines one by one, and a plurality of main bit lines to each of which two sub-bit lines among the plurality of sub-bit lines are commonly connected, one bit line being disposed between the two sub-bit lines. The semiconductor memory device further comprises a sense circuit which activates the main bit lines, a buffer which generates an activating signal which activates the sense circuit from a control signal, an address designating section which selects a memory cell indicated by an address signal among the plurality of memory cells, and a delay circuit which delays the activating signal and outputting it to the sense circuit. The address designating section activates a word line to which a memory cell indicated by the address signal is connected after some delay from the activation of a chip enable signal.
According to the present invention, the timing for activating the sense circuit approaches to the timing for activating the word line by the delay circuit. As a result, the voltage drop of the main bit lines generated at the time of reading the memory cells or charging the sub-bit lines can be inhibited. Therefore, extension of noise margin and improvement in sense speed can be achieved.
In addition, when an ON bit memory cell is selected, i.e., when the expected value of a main bit line is the low level, it is prevented to detect the main bit line as the high level before the word lines are activated. Furthermore, when an OFF bit memory cell is selected, i.e., when the expected value of a main bit line is the high level, it is prevented to detect the main bit line as the low level directly after the word lines are activated. Therefore, switching current (consuming current) due to malfunction can be reduced.
Also, if the output node of charge circuit is read and reset to the GND level at each cycle, crosstalk between main bit lines is reduced.